High Performance Low-Power Signed Multiplier

In this paper, we present a high-speed low power signed multiplier with improved booth encoders and partial product generators. Our partial product generator includes only two 2-1 multiplexers in it's critical path, while previously-designed partial product generators are using three multiplexers [1] or equivalently more logic level gates [2] in their critical paths. 4:2 Compressors connected in a Wallace tree are used for adding partial products. To reduce area and improve the speed, a distributed adder is used. After the multiplier structure designed, the best logic style for this application was selected based on comparisons made by HSPICE simulations. Then, transistor sizes were optimized to obtain a high speed, low power, and area efficient multiplier in a 0.5μm CMOS process.